PURPOSE: To prevent the destruction in the memory data at the time of multiple selection of a word line without sacrificing an access time by detecting the multiple selection of plural word lines and controlling an impedance of a bit line load.

CONSTITUTION: When two pieces or more of word lines WL0-WL511 are multiple-selected through a row decoder 14 in the state where a clock signal becomes an H, and a word line detection circuit 20 is activated, corresponding transistors(TR) TNS0-TNS511 are turned on, and a multiple selection detection signal LC is lowered. Then, the conduction of the TRs TP1, TP2 of a variable load circuit 30 are controlled, and a bit line pair BL, BLb are pulled up by pull-up TRs TN3, TN4 of the circuit 30 in an overlapped state to the conduction of the bit line load TRs TN1, TN2, and a bit line load impedance is controlled, and the potential lowering of the bit line pair is suppressed without using a delay circuit. Thus, the destruction in the memory cell data at the time of multiple selection of the word line is prevented without sacrificing the access time.