PURPOSE: To establish data held until writing is performed to a preset value, after the power supply is turned on by delaying the power supply to the load of one driving transistor from that to the load of another driving transistor.
CONSTITUTION: In the diagram, a power source VDD1 is raised to the VDD level at time t1. At this time, a gate input terminal 2 is at O level, because the VDD2 has the same electric potential as that the VSS has by the work of a delay circuit 6. Then, the power source VDD2 is raised to the VDD level at time t2. At this time, the electric potential of a terminal 2 is raised up only to the VL level, because a terminal 1 is held at the VDD level and a driving transistor T4 is conductive, and, therefore, an electric current flows to the driving transistor T4 through a load transistor T3. Therefore, a driving transistor T2 is left non-conductive, and the terminal 1 maintains the VDD level. In this way, it is sure that the terminal 1 maintains the VDD level at time T3 elapsed a prescribed time after the power supply is turned on, and thus, the uncertainly of data is eliminated.
ICHIKAWA YUKIO
HAYASHI FUMIO
SAWADA KANAME
MATSUSHITA ELECTRIC IND CO LTD
| JPS5238843A | 1977-03-25 | |||
| JPS54136236A | 1979-10-23 | |||
| JPS5438843A | 1979-03-24 | |||
| JP46017701A |