Title:
SEMICONDUCTOR SUBSTRATE WITH ALIGNMENT MARKS FOR BOTH SIDE MASKS AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS61185930
Kind Code:
A
Abstract:
PURPOSE:To make a semiconductor device production process feasible by a method wherein an alignment mark for one side processing only is utilized so that sectional shapes on both front surface side and rear surface side may be geometric in mutually analogous relations as well as the central lines of through-holes may be in parallel with the central axis of substrate. CONSTITUTION:Windows 3 with specified shape are formed into photoresit on one side of substrate 1 as necessary. Next a film of PSG, SiO2 or Si3N4 etc. resistant to anisotropic etchant is etched by well-know etchant utilizing a pattern of photoresist film 5 as a mask and after forming a mask for anisotropic etching, the photoresist film 5 is removed. Finally through holes 4 are formed by anisotropic etching process and after removing the film of PSG, SiO2 or Si3N4 etc. utilizing anisotropic etching mask, the through-holes 4 formed into both sides of silicon substrate may be utilized as alignment marks for later mask alignment.
More Like This:
| JPH06252025 | ALIGNMENT MARK FORMATION METHOD |
| JP7265020 | Stage system and lithographic apparatus |
| WO/1999/005574 | METHOD AND SYSTEM FOR PROVIDING A PROBE ARRAY CHIP DESIGN DATABASE |
Inventors:
MORIKAWA HISASHI
NISHIGUCHI KATSUNORI
NAKANO HIROYUKI
NISHIGUCHI KATSUNORI
NAKANO HIROYUKI
Application Number:
JP2586185A
Publication Date:
August 19, 1986
Filing Date:
February 13, 1985
Export Citation:
Assignee:
SUMITOMO ELECTRIC INDUSTRIES
International Classes:
G03F9/00; H01L21/027; H01L21/30; (IPC1-7): G03F9/00
Attorney, Agent or Firm:
Takashi Koshiba