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Patent Searching and Data


Title:
SEMICONDUCTOR TEST MODE CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPH04191682
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of the external terminals of a semiconductor integrated circuit by using the control terminal of a pulse generating circuit generating an one-shot pulse and the terminal of a power supply in common.

CONSTITUTION: When a voltage is linearly raised over a definite time or more at the time of the application of voltage to the terminal 1 of a power supply, the first pulse having the rising time of the voltage of the power supply and the falling time determined by the threshold voltage of the first inverter 8 and the time constant of a resistor 3 and the first condenser 5 is outputted to the inverter 8. A third output pulse having a falling time not relying in the rising time of the voltage of the power supply but determined by the threshold voltage of the inverter constituting a constant current source 4, the second condenser 7 and a buffer 10 is outputted from the buffer 10. By holding data to a D-FF 12 on the basis of the OR of the first and third output pulses, a usual use mode and an inspection mode are mutually changed over.


Inventors:
KASHIMOTO KOJI
Application Number:
JP32423890A
Publication Date:
July 09, 1992
Filing Date:
November 26, 1990
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G01R31/3185; G01R31/28; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Masuo Oiwa (2 outside)