To provide a semiconductor verification apparatus for performing EDS(Electrical Static Discharge) verification by extracting graphic information related to power supply wiring as the connection of parasitic elements or the connection of a parasitic element network and an ESD protection circuit network.

The semiconductor verification apparatus according to one embodiment verifies a semiconductor device adopting a cell base system in a chip level design. and includes: a first data generation part for generating third format data having graphic information related to power supply wiring from the first format data of mask layout data and the second format data of the cell information of automatic layout wiring; a second data generation part for generating fourth format data having power supply pin information based on the power supply pin graphic of the second format data; and a verification part for extracting the parasitic elements of the power supply wiring, and for performing verification related to the parasitic elements of the power supply wiring based on the second, third, fourth, and fifth format data.