Title:
強誘電体ランダムアクセスメモリのセンシング方式
Document Type and Number:
Japanese Patent JP7441288
Kind Code:
B2
Abstract:
Semiconductor memory devices and methods of operating the same are provided. The method of operation may include the steps of selecting a ferroelectric memory cell for a read operation, coupling a first pulse signal to interrogate the selected ferroelectric memory cell, the selected ferroelectric memory cell outputting a memory signal to a bit-line in response to the first pulse signal, coupling the memory signal to a first input of a sense amplifier via the bit-line, electrically isolating the sense amplifier from the selected ferroelectric memory cell, and enabling the sense amplifier for sensing after the sense amplifier is electrically isolated from the selected ferroelectric memory cell. Other embodiments are also disclosed.
Inventors:
Alan Devilbiss
Jonathan Lachman
Jonathan Lachman
Application Number:
JP2022180859A
Publication Date:
February 29, 2024
Filing Date:
November 11, 2022
Export Citation:
Assignee:
Infineon Technologies LLC
International Classes:
G11C11/22
Domestic Patent References:
| JP1158691A | ||||
| JP2000156090A | ||||
| JP2002100183A | ||||
| JP2004055007A | ||||
| JP2001067880A | ||||
| JP2006228291A |
Foreign References:
| WO1997035314A1 |
Attorney, Agent or Firm:
Kenji Sugimura
Mitsutsugu Sugimura
Yuro Yoshizawa
Mitsutsugu Sugimura
Yuro Yoshizawa