PURPOSE: To improve signal transmission characteristics of a bus line by connecting external terminals, which are at different array positions among plural external terminals, to the same bus line in common between mutually different semiconductor integrated circuits.

CONSTITUTION: Address terminals A1-A6 are provided as external terminals of memory devices. An address bus ABUS to which the memory devices IC1-IC6 are connected includes six bus lines a11-a6 and has a power line 30 for supplying high-potential side electric power Vcc to the memory devices IC1-IC6 and a ground line 40 as a reference voltage line. Then external terminals which are at different array places among the address terminals A1-A6 are connected to the same bus line in common among the mutual different memory devices. Therefore, variance in capacity among the bus lines a1-a6 is nearly eliminated and the maximum capacity on the bus lines is reducible, so that the address signal transmission characteristics can be improved.