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Title:
SEPARATION OF PCI AND EISA BY CONTROL AND MASKING OF INTERRUPTION LINE
Document Type and Number:
Japanese Patent JPH10334043
Kind Code:
A
Abstract:

To enable the continuous operation of a distributed computer system by providing a system managing processor and a system managing module provided with an arbiter and a system managing unit including a monitor logic and an interruption routing logic.

A computer system 5 is provided with a host subsystem 25 equipped with a host central processing unit 10 and the system managing module(SMM) 100 is provided with the system managing processor(SMP). A system managing center(SMC) is provided with a PCI interface, PCI arbiter, logic monitor, interruption routing logic, address translation logic, system managing register, local bus controller, system managing processor controller and SM memory controller. Then, the status of SMR device is monitored and operation is performed as a bridge between a PCI bus 50 and a system managing local bus.


Inventors:
TAVALLAEI SIAMAK
HULL DANIEL S
Application Number:
JP3192298A
Publication Date:
December 18, 1998
Filing Date:
January 05, 1998
Export Citation:
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Assignee:
COMPAQ COMPUTER CORP
International Classes:
G06F11/20; G06F11/00; G06F11/30; G06F11/34; G06F13/24; G06F13/362; G06F11/273; (IPC1-7): G06F13/362; G06F11/20; G06F11/30; G06F13/24
Attorney, Agent or Firm:
Kazuo Shamoto (6 outside)