To provide a high speed as well as also surely perform state transition of a sequencer main body by providing a sampling circuit or the like, which samples a counter output in a timing that is asynchronous with a counter output timing and outputs a control signal that transits the state of the sequencer main body.

A gray code counter part 1 performs count processing by an input of a trigger signal 'a' and outputs gray code count data 'b' to a sampling circuit 2. The circuit 2 samples the data 'b' from the part 1 by an input a sampling clock 'c' of a timing, that is asynchronous with the signal 'a' and outputs a control signal 'd' to transits the state of a sequencer body. As for the clock 'c' that is used by the circuit 2, a fast clock signal can be used without having to be conscious of the working of a gray code counter in the preceding stage, and fast state transition to a desired state becomes possible.