PURPOSE: To realize the output of the data on a double series of a part (a) containing (m) words and a part (b) containing (l) words in the prescribed delay timing, by using an (m×2+l)-word memory and an (m×2+l×2)-ary counter which produces the address of the memory.
CONSTITUTION: An (m×2+l×2)-ary counter 2 applies the initial reset at the head part of a first data on a part (a) of an input signal train and then writes successively the data into an (m×2+l)-word memory 1. The counter 2 is reset at an (m+1) address by the (m×2+l)-th clock. Here a part (b) preceding by a unit is already written in an area covering the (m+1) address through the (m+l) address and the data on these parts (b) are successively read out. Thus the data on the part (b) is outputted with a delay by an amount equal to one unit. Hereafter the input/output of data is repeated in the same way. Thus it is possible to obtain the input signal trains of the double series consisting of the part (a) containing (m) words and the part (b) containing (l) words with delays by the amounts equal to two units and one units in both parts (a) and (b) respectively.
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