PURPOSE: To reduce the circuit scale by allowing a start signal enerating section to generate a start signal and allowing a counter section to count the consecutive time of the operation started by the start signal, and by using in common for a counter for sequential control and a counter for counting purpose.

CONSTITUTION: When a reset signal RST is released at a time T1, a flip-flop 131 is set corresponding to the rising of a clock pulse CK1 appearing first in a clock signal CKS after the time T1. A logic circuit section 134 restores an output 13d to an L level L1 to open a switch S3, and outputs an output 13a being at an H level H2 to an external device, thereby starting a rage finding operation. When the value of a counter section 12 reaches '8', a flip-flop 133 is set. The same operation is repeated by bringing the reset signal RST to an H level so as to set the initializing state, then to bring the level to an L level.