PURPOSE: To attain a high-speed operation with less number of active elements by cascade-connecting plural stages of a state-maintaining circuits and inputting clock signals in the other plural ends of the input terminals of each state- maintaining circuit.

CONSTITUTION: An inversion output type 2 input state maintaining circuits 11-15 are cascade-connected only plural stages, and plural input terminal ends A of each of the state-maintaining circuits 11-15 are connected to the output terminals Q of each preceding stage of the state maintaining circuits. And, an input signal D is inputted into the one input terminal ends A of a first level of the state maintaining circuit 11, the input terminal ends A of a second stage through a last stage of the state-maintaining circuits 12-15 are connected to the output terminals Q of each of the preceding stages of the state maintaining circuits, and from the output terminals Q of the last stage of the state maintaining circuit 15, an output signal Q is outputted. In the opposite input terminal ends B of each state maintaining circuit 11-15, a common clock signal C is inputted. Thus, the sequential logic circuit is composed of less number of active elements, and the high-speed operation is made possible.