Title:
SEQUENTIAL MEMORY AND METHOD FOR INPUTTING AND OUTPUTTING DATA WITH SEQUENTIAL MEMORY
Document Type and Number:
Japanese Patent JPH06131154
Kind Code:
A
Abstract:
PURPOSE: To achieve a high data speed by using a memory for which a sequential memory is interleaved by relating plural output buffers.
CONSTITUTION: A data access control circuit 18 and a bank selection circuit 20 control the order of writing and reading memory banks 12a and 12b. Plural output buffer control circuits 22a and 22b read the data word immediately after writing the data word in this sequential memory 10.
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Inventors:
MORISU DEII UOODO
KENESU ERU UIRIAMUZU
KENESU ERU UIRIAMUZU
Application Number:
JP33369591A
Publication Date:
May 13, 1994
Filing Date:
December 17, 1991
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G11C7/10; G06F5/16; (IPC1-7): G06F5/06
Attorney, Agent or Firm:
Akira Asamura (3 outside)