Title:
SERIAL COMMUNICATION CONTROL SYSTEM AND SERIAL COMMUNICATION CONTROL METHOD
Document Type and Number:
Japanese Patent JP3431071
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce CPU processing and to improve system capability by providing a parallel bus, a serial bus and the signal line of an interruption signal which informs CPU of communication termination from a parallel/serial conversion port.
SOLUTION: The CPU 13 of a serial communication control system 11 controls the system 11. A parallel/ serial conversion port 14 executes communication by the serial data of the system 11 and a target 12. A parallel bus 15 transfers data between CPU 13 and the parallel/serial conversion port 14. A serial bus 16 transfers data between the parallel/serial conversion port 14 and the target 12. The signal line 17 of an interruption signal informs CPU 13 of communication termination from the parallel/serial conversion port 14. Thus, processing time, especially that the CPU 13 of the system requires, is reduced at the time of executing communication with the outside and therefore the processing capability of the whole system can be improved.
Inventors:
Kazuyuki Kobayashi
Application Number:
JP12224199A
Publication Date:
July 28, 2003
Filing Date:
April 28, 1999
Export Citation:
Assignee:
NEC
International Classes:
G06F13/00; H03M9/00; H04L13/10; H04L29/10; (IPC1-7): H04L29/10; G06F13/00
Domestic Patent References:
| JP63202161A | ||||
| JP10178537A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)
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