Title:
シリアル通信装置,シリアル通信方法,シリアル通信のための記憶媒体およびプログラム
Document Type and Number:
Japanese Patent JP4803891
Kind Code:
B2
Abstract:
At the time when the control signal line of a printer controller is connected to the input terminal of a three-state buffer, the control signal line is connected also to the D input terminal of the flip-flop that operates according to the FFCK clock. The control signal of Q output signal of the flip-flop is inputted into the AND gate circuit, and the output signal of the gate is inputted into the control terminal of three-state buffer. Accordingly, by synchronizing the signal to the place where the level of control signal line starts, the level of data signal line changes from level 1 to the level of output. After that, waveform rounding that is generated at the time of releasing the signal line is reduced to enable higher communication speed.
Inventors:
Kazuo Goto
Application Number:
JP2001067443A
Publication Date:
October 26, 2011
Filing Date:
March 09, 2001
Export Citation:
Assignee:
Canon Inc
International Classes:
G06F13/12; G06F13/38; G06F13/42
Domestic Patent References:
| JP11154045A | ||||
| JP8228144A | ||||
| JP9054752A | ||||
| JP7049832A | ||||
| JP2000235794A | ||||
| JP63061526A |
Attorney, Agent or Firm:
Patent Business Corporation Tani/Abe Patent Office
Yoshikazu Tani
Kazuo Abe
Yoshikazu Tani
Kazuo Abe