PURPOSE: To prevent receiving data from being missed at a terminal by sending a communication clock from the terminal to a host computer, and controlling run/stop from the terminal side.

CONSTITUTION: When the 1st byte of receiving data RD is transmitted from the host computer 10 to the terminal 20, a serial interface 2 enables an RIRQ signal and outputs an interruption request for serial reception to a terminal processor 3. Simultaneously, a d type FF circuit 8 is reset by the RIRQ signal, the communication clock from a gate 11 is suspended and data sending from the computer 10 is temporally stopped. After completing the task in processing, the processor 3 enables a read signal R and enters the 1st byte of the data RD through a data bus. Simultaneously with the input, the clear signal of the circuit 8 is released. The circuit 8 is set up by a signal from a clock circuit 9 and a communication clock is sent again from the gate 11. The 2nd byte and after are read to the terminal 20 side in the same manner.