To allow a decoder circuit in a serial data processor circuit to be inspected even if the number of address data increases.

The processor circuit comprises: a serial-parallel converter circuit 10 for converting serial data into parallel data; first and second address decoders 20, 21 having the same constitutions for decoding address data A0-An-1 converted into parallel data by the serial-parallel converter circuit 10; a match and comparison unit for detecting the matching of decode outputs therefrom; and data registers 30-1 to 30-X for writing in data D0 to Dm-1 designated according to the decode output from the second address decoder 21 after conversion to the parallel data by the serial-parallel converter circuit 10.