PURPOSE: To allow the receiver to cope with even a multiplex line by means of the same hardware by using a prescribed bit number of FIFO memory for the synchronism between a sampling clock and a system clock of a data processing section.

CONSTITUTION: An input serial data from channels CH1∼CH8 is inputted in parallel to an FIFO memory 11 one by one bit at each channel by a sampling clock. Since an 8-bit parallel type FIFO memory 11 is used in this example, the data for 8 channels' share is stored. An FF1 is operated in synchronizing with the system clock and then a signal BFF' is outputted in synchronizing with said system clock. A signal from the FF1 is given to the FIFO memory 11 and an RAM12 via a gate G1 and then the content of the FIFO memory 11 transferred in the way of direct memory access (DMA) to the RAM12.