PURPOSE: To receive data with a clock pulse having a comparatively low frequency and to convert the received data into parallel data.

CONSTITUTION: A clock generating circuit 10 generates a clock signal whose frequency is twice the serial data transmission frequency, a data reception section 1 detects serial data in a timing by the clock signal and converts the data into parallel data, which are outputted. On the other hand, a clock signal whose phase is delayed by 180° with respect to the clock signal is generated by an inverter 11, a data reception section 2 detects the serial data in a timing by the clock signal and converts the data into parallel data. Then a data selection section 3 discriminates which of both the reception data by both reception sections are more proper and the parallel data outputted from the selected side are finally outputted.