PURPOSE: To perform multiplication which does not require a guard bit for sign extension for a multiplicand and to shorten a computation time by providing a sign extending circuit and a circuit which inserts output data of the sig extending circuit into the MSB of a partial sum to a next stage.

CONSTITUTION: An and circuit 3 calculates a partial product X.yi and a full- adder circuit 4 adds the partial product X.yi and a partial sum PPSi from the front stage together to generate a partial sum (X.yi+PPSi). An F/F circuit 5 with a cleaning function holds the carry of the full-adder circuit 4, and the sign extending circuit 6 consists of a 1-bit full-adder circuit or 3-input exclusive OR circuit, etc., and inputs the output of the AND circuit 3, the partial sum PPSi from the front stage, and the carry of the full-adder circuit 4 to calculate an extended sign bit. A selecting circuit 7 selects the partial sum outputted from the full-adder circuit 4 and the extended sign bit outputted from the sign extending circuit 6 with a word synchronizing signal WCK. Further, an output terminal 9 is provided and OX, Oy, Opps, and Osck outputs X, Y, PPSi+1, and WCK to multiplying cells of the same constitution connected to rear stages respectively.