To eliminate the exchange of a signal between super-high speed P/S converting ICs and to prevent a malfunction by executing parallel/serial conversion by means of two steps.

1ch10-bit signals 1-1 to 1-10 are inputted to a latch 4-1 so as to output parallel signals 5-1 to 5-10, 2ch10-bit signals 2-1 to 2-10 are inputted to the latch 4-2 so as to output the parallel signals 6-1 to 6-10 and 3ch10-bit signals 3-1 to 3-10 are inputted to the latch 4-3 so as to output the parallel signals 7-1 to 7-10. Bit change is executed in a bit changing part 12 concerning the parallel signals and they are outputted after becoming the parallel signals 13-1 to 13-10, 14-1 to 14-10 and 15-1 to 15-10. The parallel signals where the bits are changed are converted into serial signals 17-19 by corresponding first P/S converters 16-1 to 16-3 so as to be outputted. Then, the serial signals 17-19 are inputted to the second P/S converter 20 and outputted as the serial signal 21.