To rewrite data of one part of a row at high speed in a DRAM.
This circuit is provided with a dynamic cell block 11, a sense amplifier sensing the data of the cell block 11, a latch 2 for storing the data, a data transfer gate performing data transfer between the sense amplifier 3 and the latch 2, and a byte-write-mask circuit block 1 transferring the data to the sense amplifier 3 by controlling only the data transfer gate corresponding to the latch in which data is written out of the latch 2. Only a transfer gate corresponding to the latch 2 in which the data are written by the byte-write-mask circuit block 1 is opened, when the data are written in the cell block 11 by transferring the data to the sense amplifier 3 from the latch 2, as only the required data are written in the latch 2, needless data writing in the latch is not required, high speed transfer of data for the cell block 11 can be performed.
| JPS6416124 | PARALLEL/SERIAL CONVERTING CIRCUIT |
| WO/2000/064056 | CIRCUIT ARRANGEMENT FOR PARALLEL/SERIAL CONVERSION |
| JPH07101551 | [Title of Invention] Video storage device |
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
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