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Patent Searching and Data


Title:
SERIAL-PARALLEL SIGNAL CONVERSION CIRCUIT
Document Type and Number:
Japanese Patent JPH02222219
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of ICs built in a connector with a circuit constitution by constituting a circuit such that the signals are inputted respectively from many parallel signal input/output terminals and the signals are respectively outputted from them in bidirectional way.

CONSTITUTION: A circuit 10 is so constituted that the signals are outputted via parallel signal input/output terminals 23-30 respectively ad the signals are inputted via them respectively in bidirectional way. A time series signal (command signal) inputted from a control computer via a time series signal input/ output terminal 15 is outputted to the relevant parallel signal input/output terminals 23-30 via a command latching circuit 41 and a bidirectional buffer circuit 43. Moreover, the signal inputted to a gate circuit 44 via the bidirectional buffer circuit 43 from the parallel signal input/output terminals 23-30 is sent as a response signal via an OR circuit 45 and the terminal 15 sequentially. Thus, in the case of incorporating the IC provided with the circuit constitution into a connector, the number of ICs to be built in is reduced.


Inventors:
TAKAGI SHINICHI
Application Number:
JP4269389A
Publication Date:
September 05, 1990
Filing Date:
February 22, 1989
Export Citation:
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Assignee:
AMP JAPAN
International Classes:
H03M9/00; (IPC1-7): H03M9/00
Attorney, Agent or Firm:
Seiji Yanagida (1 person outside)