PURPOSE: To realize the high-efficiency data process as well as the high-speed data transmission by varying the clock velocity to the transmission side according to the decision results of the necessary process time for the reception data.

CONSTITUTION: At transmission side 1, the data supplied from data line 91 is sent out to line 102 via memory circuit 11 and parallel-series converter circuit 21 to be supplied to the processor at the reception side 2 via series-parallel converter circuit 32, memory circuit 42 and data line 92 respecitively. The velocity of the reception data is monitored through decoder circuit 8, and the monitor output controls the selector circuit 7. Then the output of clock generator 5 along with its divided (6) output are selected to be delivered and then to be supplied to the transmission side via line 104. In this case, if the data featuring a long process time is detected through decoder 8, the divided (6) clocks are selected and transmitted