PURPOSE: To surely attain high-shake by providing a locking circuit of a clock line at slave reception and an interruption circuit at slave transmission so as to allow a master CPU to recognize the state of a slave CPU.
CONSTITUTION: A slave CPU 9 recognizes it that a reception data is stored in a reception data register 6 at slave reception and the data and subject to wired-AND processing through a control circuit 3, a GCL(b) is locked to bring the master CPU 10 in the standby state. In case of writing a transmission data from the slave CPU 9 to a transmission data register 5 at the slave transmission, interruption (i) takes place through an interruption circuit 8 and the transmission data written in the transmission data register 5 is recognized by the master CPU 10. Thus, sure hand-shake is realized between the master CPU and the slave CPU in this way.
SHINPO HIROYASU
UNEMURA TOYOAKI
SAKAMOTO MASARU
MORII TAKASHI
FUKUDA CHIKA
