Title:
SERIES REGULATOR POWER SUPPLY CIRCUIT
Document Type and Number:
Japanese Patent JP3750787
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve the removing ratio of ripples included in the power supply voltage of a series regulator power supply circuit to be used as a power supply for electronic equipment or the like.
SOLUTION: The MO of a PMOS FET is used as an output, and the intermediate voltage between resistors R1, R2 connected between the PMOS FET and ground is compared with a reference voltage applied from a reference voltage circuit 2 and the output stage 3 of an amplifier circuit 1 using input power supply VIN or an output as a power supply (terminal 5) is provided with a constant current source with a filter in order to control the MO by the circuit 1 and output required output voltage. Thus the removing ratio of ripples can be improved by allowing high frequency ripples included in the power supply (terminal 5) of the circuit 1 to pass the output.
Inventors:
Kimiyoshi Miso
Akira Hyogo
Hideki Nakazawa
Daishi Koji
Keitaro Sekine
Akira Hyogo
Hideki Nakazawa
Daishi Koji
Keitaro Sekine
Application Number:
JP2000006579A
Publication Date:
March 01, 2006
Filing Date:
January 14, 2000
Export Citation:
Assignee:
Fuji Electric Device Technology Co., Ltd.
International Classes:
G05F1/10; G05F1/56; H02M3/155; (IPC1-7): G05F1/10; H02M3/155
Domestic Patent References:
| JP10303658A | ||||
| JP8272461A |
Foreign References:
| US5949274 |
Other References:
代市 幸司、他3名,低電圧動作シリーズレギュレータの低周波領域でのリプル除去率を改善するOPアンプの構成,電子情報通信学会論文誌,日本,社団法人電子情報通信学会,1999年 6月25日,第J82-C-II巻,第6号,p.354-355
Attorney, Agent or Firm:
Iwao Yamaguchi
Yoshihide Komada
Kiyoshi Matsuzaki
Yoshihide Komada
Kiyoshi Matsuzaki