Title:
SHALLOW JUNCTION SOG PROCESS
Document Type and Number:
Japanese Patent JP3466244
Kind Code:
B2
Abstract:
PURPOSE: To prevent a lattice defect and a leakage current from being generated in junctions by a method wherein first and second SOG layers, which respectively contain a first dopant and a second dopant, are rotated on a semiconductor substrate and the dopants are diffused in the substrate to form the first and second junctions.
CONSTITUTION: A SOG doped with sulfur, which is in the state of a liquid, is spin-coated on a silicon wafer 12. A layer 14 is formed. A centrifugal force is generated by a spin, most of the liquid sulfur is separated from a polymer by the centrifugal force, the polymer is dried and the flat surface of the polymer is formed. It is preferable that the thickness of the layer 14 on the flat surface is about 1500 angstroms. Then, a masking operation is carried out using etching- resisting emulsion. After that, one part of the layer 14 is prevented from being removed by etching. In the case of a MOSFET, a masking operation for an N+ source and a P+ drain is carried out.
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Inventors:
Daryl Duane John Allman
Dim-Lee Kwong
Dim-Lee Kwong
Application Number:
JP28627593A
Publication Date:
November 10, 2003
Filing Date:
October 22, 1993
Export Citation:
Assignee:
Hyundai Electronics America
NC International Inc.
Symbios Incorporated
NC International Inc.
Symbios Incorporated
International Classes:
H01L21/225; H01L21/316; H01L21/336; H01L21/8238; H01L27/092; H01L29/78; (IPC1-7): H01L21/225; H01L21/316; H01L21/336; H01L21/8238; H01L27/092; H01L29/78
Domestic Patent References:
| JP5530861A |
Other References:
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Attorney, Agent or Firm:
Yoshiaki Nishiyama