PURPOSE: To omit consciousness of the address space of a shared memory within a cache memory and also to eliminate the need for the control command for cache memory received from software, by referring to one signal line led from the shared memory.

CONSTITUTION: This shared memory system contains a shared memory 20 which is connected between the 1st common bus 100 where the I/O control parts 50W70 and a main memory 40 are connected to a CPU 30 via a cache memory 10 and the 2nd common bus 200 to which only I/O control parts 80 and 90 are connected. Then the memory 20 receives access independently from the bus 100 or 200 and outputs a reference signal meaning the read access of its own to the first bus 100 together with the data to be sent back from the bus 100 in a read access mode. This signal 1 functions to inhibit the replacement action of the memory 10 caused by a no-hit state.