PURPOSE: To increase the shifting speed by using a memory to store the data indicating the propriety for execution of a shift action and using the data stored in said memory to control the shift action of a shift register.

CONSTITUTION: An up/down counter 2 is set in a count-up mode, and the address data n0 is supplied through a signal line L2 and stored. An address n0 is supplied to a ROM5 through a signal line L6, and the data "1" stored in the address n0 is read out via a signal line L7 and supplied to an AND gate circuit 3. When a clock pulse is supplied via a signal line L1, a shift instruction is delivered to a shift register 1 through the circuit 3. Thus a shift action is carried out. At the same time, the counter 2 counts up the data n0 and stores newly (n0+1). Hereafter the same operation is repeated. When the address data stored in the counter 2 reaches (n0+N), the data "0" is delivered through lines L6 and L7. Then the circuit 13 is cut off and the shift action is stopped.