PURPOSE: To simplify circuit constitution by allowing one shift register to cover both a function of an input side shift register and an output side shift register.

CONSTITUTION: An input serial data is inputted to an S1 terminal of 1st shift register SR 5 via an FF circuit 4. Then a load signal is inputted to an LD terminal of the SR 5 and a parallel data is inputted from the SR 5 to a 2nd shift register SR 6. The data inputted to the SR 6 is outputted to via an 50 terminal as a serial data to a data processing circuit 7, where a prescribed arithmetic logical operation is applied and the result is given to an SI terminal of the SR 6. Then a parallel data is outputted from the SR 6 to the SR 5. Thus, the data inputted to the SR 5 is outputted from the terminal 80 of the SR 5 and fed to a circuit of the post stage as an output data. The functions of an S/P conversion circuit and a P/S conversion circuit are processed by one set of data conversion circuit comprising the circuit 4 and the SR 5 in this way.