PURPOSE: To attain the high speed of an operation by making the master circuit of a D flip-flop have a selecting function selecting either one of parallel input data and reducing a delay in a shift register.

CONSTITUTION: In a case that the logical value of a selecting signal S is '1', the output logical value of a two input NOR 55 goes to '0' to make an FET 53 to be an OFF state and one pair of switching transistors 51, 52 inputting data B and/B do not operate. besides, the inverse clock signal/CK is outputted from the output terminal of a two input NOR 54. Further, in a case that the logical value of the signal S is '0'. the output logical value of the two input NOR 54 goes to '0' to mask an FET 18 to be in an OFF state and one pair of transistors 16, 17 do not operate. On the other hand, at this time, the signal/CK is outputted from the output terminal of the two input NOR 55. In above operations, in both cases where logical value of the signal is '1' and '0', the signal passes only two pieces of gates in a master circuit 210 and a slave circuit 200b until data are inputted to the shift register and are outputted from the register.