Title:
SHIFT REGISTER CIRCUIT AND IMAGE DISPLAY DEVICE
Document Type and Number:
Japanese Patent JP2014127221
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a shift register circuit that prevents a drop in potential of an output signal.SOLUTION: A shift register circuit 20 includes a transistor 1 that decreases a potential of a node 22 in response to an increase in potential of a node 21, and a transistor 2 that decreases a potential of a node 23 in response to an increase in potential of the node 21. The shift register circuit 20 further includes a transistor 3 that decreases a potential of the node 21 in response to an increase in potential of the node 22, and a transistor 4 that decreases a potential of the node 21 in response to an increase in potential of the node 23. The shift register circuit 20 also includes a transistor 5 that outputs OUTin response to an increase in potential of the node 21 when a pulse of CLKflows.
Inventors:
ICHIMURA TERUHIKO
Application Number:
JP2012286113A
Publication Date:
July 07, 2014
Filing Date:
December 27, 2012
Export Citation:
Assignee:
KYOCERA CORP
International Classes:
G11C19/28; G02F1/133; G09G3/20; G09G3/30; G09G3/36; G11C19/00; H01L51/50
Domestic Patent References:
| JP2006189762A | 2006-07-20 | |||
| JP2007004167A | 2007-01-11 |
Attorney, Agent or Firm:
Hiroaki Sakai