Title:
SHIFT REGISTER DATA TRANSFER CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS5214323
Kind Code:
A
Abstract:
PURPOSE: When there is some difference between the central processor unit bit transfer speed and that of the external memory unit, to reduce transfer time by harmonizing these speeds.
Inventors:
MISE KEISUKE
AMANO TSUNEO
AMANO TSUNEO
Application Number:
JP9042175A
Publication Date:
February 03, 1977
Filing Date:
July 24, 1975
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F5/08; G11C19/08; (IPC1-7): G11C19/00
Domestic Patent References:
| JPS4887741A | 1973-11-17 | |||
| JPS4974848A | 1974-07-19 | |||
| JPS4974850A | 1974-07-19 |