To prevent gradual degradation in the level of a signal to be inputted from each stage of a shift register to the next stage.

A first stage RS1 (1) comprises five n-MOSs 201, 202, 203, 205 and 206. When the level of a signal Φ1 becomes a high level, the n-MOS 201 is turned on, Thus, a start signal IN supplied from outside is supplied to the gate of the n-MOS 205 to make the level of a wiring capacity C5 high. The level of the wiring capacity C5 is kept to be high until the n-MOS 201 is turned on next. Thus, the n-MOS 205 keeps an on-state. Since the level of a wiring capacity C2 is also high in this case, an n-MOS 202 is turned on to make the level of a wiring capacity C6 low, and an n-MOS 206 is kept to be in an off state. Thus, while the level of a signal CK1 is high, an output signal OUT1 which is nearly equal to the level of the signal CK1 is outputted from an output terminal OT1.