Title:
SHIFT REGISTER MEMORY
Document Type and Number:
Japanese Patent JPS5744293
Kind Code:
A
Abstract:
This serial to parallel to serial (SPS) charge coupled device (CCD) shift register memory has a serial output shift register with stage gate electrode structures that are interdigitated with the gate electrode structures of each last stage of a plurality of parallel shift registers to transfer interlaced data bits from the parallel shift registers to the serial output register in a sequential order. This is done without employing a fixed voltage midway between the highest clock voltage and reference potential in the parallel registers in what is commonly called a midway store to regulate the transfer of data to the interdigitated gate electrode structures.
Inventors:
JIYON JIYOSEFU BAAN
JIYAN MARUKU FUEERU
IERANDEYUURU RANGANASA GOPARAK
JIYAN MARUKU FUEERU
IERANDEYUURU RANGANASA GOPARAK
Application Number:
JP5637081A
Publication Date:
March 12, 1982
Filing Date:
April 16, 1981
Export Citation:
Assignee:
IBM
International Classes:
G11C27/04; G11C19/28; H01L21/339; H01L27/105; H01L29/762; (IPC1-7): G11C19/28; G11C27/00; H01L29/76