PURPOSE: To surely transfer data even when registers are connected in cascade without complicating clock control in a shift register.

CONSTITUTION: A master flip-flop(FF) 1 is operated in synchronization with a clock CL. A save FF 2 is operated synchronously with the clock CL and delayed by a half period of the clock CL in reference to the operation of the master FF 1 when a set signal or a reset signal is not imparted to it and, when the set or the reset signal is imparted, it is set or reset based on these signals. A parallel input buffer 5 outputs a set signal or a reset signal in compliance with the respective bits Bit1,...,BitN (N is an integer larger than two) of parallel data to the respectively corresponding slave FFs 2 when a latch enable signal: the inverse of LE is activated. A control circuit 6 operates a FF 7 for delaying the output in synchronization with the master FF 1 when the latch enable signal: the inverse of LE is inactive and the FF 7 for delaying the output is operated independent of the clock CL when the latch enable signal: the inverse of LE is active.