Title:
【発明の名称】VLSI回路の欠陥テスト方法
Document Type and Number:
Japanese Patent JP3104735
Kind Code:
B2
Abstract:
A method based on continuous optimization techniques for generating test vectors for use in testing VLSI circuits includes representing digital circuits as smooth functions. The test generation problem is formulated as the minimization of the objective function over a hypercube in Euclidean space. The dimension of the space is equal to the number of primary inputs of the circuit. The smooth function is optimized inside a convex polytope using a variant of gradient descent and line search strategies. The solution starts at the center of the hypercube and follows a trajectory to one of the corners of the hypercube that corresponds to a test vector. Once the test vector is determined by this method, electrical signals corresponding to the test vector are applied to the inputs of the VLSI circuits. The outputs of the VLSI circuit are monitored in order to locate defects in the circuit. The representation of the logic gates as a continuous family of functions enables the method to quickly find an optimal solution to the test generation problem.
Inventors:
Sri Matt T. Charadaher
Eiger Livin
Eiger Livin
Application Number:
JP4110695A
Publication Date:
October 30, 2000
Filing Date:
February 28, 1995
Export Citation:
Assignee:
NEC
International Classes:
G01R31/317; G01R31/3183; (IPC1-7): G01R31/3183
Attorney, Agent or Firm:
Yosuke Goto (1 person outside)