Title:
SHOCK PREVENTING CIRCUIT
Document Type and Number:
Japanese Patent JPS61195401
Kind Code:
A
Abstract:
PURPOSE:To suppress the sudden change of a control signal by detecting the deviation between an input signal and a holding signal through a signal selecting circuit and using the value obtained by adding or subtracting the fixed value to or from the holding signal as an output signal when said deviation exceeds a fixed level. CONSTITUTION:A shock preventing circuit suppresses the sudden change of an error voltage (input signal) SI and obtains an output signal SO to turn a rotary barrel. Then a signal selecting circuit 79 is provided to the shock preventing circuit. The circuit 79 consists of the 1st sample holding circuit 70, a deviation detector 71, an adder 74, an absolute value circuit 75, a deviation setting unit 76, a comparator 77 and a gate circuit 78. Then the input signal SI is supplied to the circuit 70 and the detector 71, and the output signal SO is supplied to a rotary device and the 2nd sample holding circuit 72. While the deviation between the signal SI and the holding signal SA is detected. When this deviation exceeds a fixed level, the fixed value SB is added to or subtracted from the signal SA as the signal SO. While the signal SI is delivered as it is when said deviation is less than the fixed level.
Inventors:
KODERA MASASATO
AIZAWA YASUO
AIZAWA YASUO
Application Number:
JP3686185A
Publication Date:
August 29, 1986
Filing Date:
February 26, 1985
Export Citation:
Assignee:
NIIGATA ENGINEERING CO LTD
International Classes:
G05B1/01; G05B5/01; (IPC1-7): G05B1/01
Domestic Patent References:
| JPS59105038A | 1984-06-18 | |||
| JP49053195B | ||||
| JPS5576401A | 1980-06-09 | |||
| JPS50155881A | 1975-12-16 |
Attorney, Agent or Firm:
Masatake Shiga