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Title:
SIGNAL ANALOGIZING CIRCUIT FOR SAMPLE HOLD OUTPUT SIGNAL
Document Type and Number:
Japanese Patent JPS5834622
Kind Code:
A
Abstract:

PURPOSE: To make analog signal without using a low-pass filter by taking difference between a staircase wave signal and a staircase wave signal made by delaying the staircase wave signal and adding a signal obtained by integrating the differential signal for every period to the delayed staircase wave signal.

CONSTITUTION: An FM composite signal 1 is converted to staircase wave through a buffer 2 and a staircase wave generating circuit U. This signal passes through the first sample hold circuit V, a buffer 8 and the second sample hold circuit V and delayed by phase difference of two-phase pulse of a pulse generating circuit 3. The sum of output of the circuit U and output of the circuit W inverted in an inversion circuit 14 is obtained by an adder 15 and applied to an integrator 16. Sampling pulse of the circuit 3 is added to the integrator 16 and reset by this pulse. Output of the integrator 16 is added to staircase wave output of the circuit W, and smooth waveform is obtained from the adder 18.


Inventors:
OGAWA ATSUSHI
Application Number:
JP13242381A
Publication Date:
March 01, 1983
Filing Date:
August 24, 1981
Export Citation:
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Assignee:
KENWOOD CORP
International Classes:
H03K9/02; (IPC1-7): H03K9/02
Domestic Patent References:
JP45034653A