To provide a signal arithmetic unit that detects the fault of an input signal processing circuit, while keeping reception of an input from a signal source.
An input signal processing circuit 12 processes an input signal from an external signal source 14, a CPU 13 receives a signal from the input signal processing circuit 12 and conducts the arithmetic operation of subtracting a test signal from the signal, a test signal generating circuit 16 generates the test signal, and an adder 18 adds the test signal to the input signal. Thus, the input signal processing circuit 12 receives a signal which is a sum of the test signal from the test signal generating circuit 16 and the input signal, without having to disconnect the connection between the signal source 14 and the adder 18.
SAITO KOJI
NEMOTO KIICHIRO
Next Patent: DIGITAL SELF-CORRECTING SYSTEM FOR ANALOG-TO-DIGITAL CONVERTER CONNECTED TO PIPELINE