Title:
信号変換回路、ＰＬＬ回路、遅延調整回路及び位相制御回路
Document Type and Number:
Japanese Patent JP5831995
Kind Code:
B2
Abstract:
A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTC 8 generates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.
Inventors:
Toru Nakura
Kunihiro Asada
Kunihiro Asada
Application Number:
JP2013518001A
Publication Date:
December 16, 2015
Filing Date:
May 23, 2012
Export Citation:
Assignee:
Aika Design Co., Ltd.
International Classes:
H03K5/26
Domestic Patent References:
| JP9046195A | ||||
| JP7240670A | ||||
| JP61227422A |
Attorney, Agent or Firm:
Koji Hadachi