PURPOSE: To reduce the circuit scale with simple constitution by providing a parallel input serial output shift register having an input terminal, an inverting circuit and a timing circuit and applying the parallel serial conversion and the insertion of a complementary code simultaneously.
CONSTITUTION: Parallel data D0-D4 are led to input terminals P1-P5 of a shift register 10 as they are. Moreover, after the one bit D0 is inverted logically at an inverter 30, it is led to the input terminal P0 of the register 10 as the complementary code. Then the data D0-D4 and the complementary code are loaded to the register 10 synchronously with the arrival timing of the data D0-D4 from a timing circuit 20, e.g. synchronously with a load signal LOAD. Then the data are read synchronously with a clock CLK 1 and outputted as serial data SD in the order of the data D0, D1, D2, D3, D4 while taking the complementary code as the head.
ICHIKI TOYOHIKO
YOROZU MASATOSHI
KUNISHIGE SEIJI
SHIBAGAKI TARO
SHIMIZU FUMIHIKO
FUJIOKA FUMIO
KONDO TOSHINORI
TOSHIBA CORP
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