PURPOSE: To send a signal synchronized surely to an output highway by storing tentatively a parallel binary signal into a shift register synchronously with a clock signal being a reference again and outputting the binary signal to the output highway simultaneously synchronously with the reference clock signal.

CONSTITUTION: A conversion latch circuit 100 converts a serial binary signal sent from an input highway 1 into a parallel binary signal and latches it and outputs it synchronously with a series binary signal S1. A latch circuit 200 latches a parallel binary signal P100 outputted from the conversion latch circuit 100 and holds and outputs it synchronously with a referenced clock signal. An arrangement setting circuit 300 changes the bit arrangement of a parallel binary signal P200 outputted from the latch circuit 200 into a designated form and outputs the result. Then a shift register 400 latches a parallel binary signal P300 outputted from the arrangement setting circuit 300 and sends it one by one bit to one or plural output highways 9 synchronously with the referenced clock signal. Thus, the signal synchronized surely is sent to the output highway.