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Patent Searching and Data


Title:
SIGNAL CONVERTER
Document Type and Number:
Japanese Patent JPS626536
Kind Code:
A
Abstract:

PURPOSE: To eliminate substantially beat noise with a simple circuit constitution by providing a jitter mixing means to apply FM modulation to a control clock thereby adding substantially jitter.

CONSTITUTION: A bit clock from an input terminal 2 is fed to a jitter mixing circuit 30, where the clock is FM-modulated and jitter is added. The bit clock added with the jitter is fed to the clock terminal of a flip-flop circuit 31 to add substantially jitter to a digital data, a converting instruction and a word clock delivered from the flip-flop circuit 31 to a D/A converter 5 sequentially when the bit clock is applied. Thus, the data and the clock applied from input terminals 1∼4 are added with jitter to move momentarily the frequency and the beat spectrum is made spread in white noise form to eliminate substantially the beat noise.


Inventors:
EBATA KAZUYOSHI
Application Number:
JP14548185A
Publication Date:
January 13, 1987
Filing Date:
July 02, 1985
Export Citation:
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Assignee:
SONY CORP
International Classes:
H03M1/04; (IPC1-7): H03M1/04
Attorney, Agent or Firm:
Sada Ito