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Title:
SIGNAL DECODER AND SIGNAL DECODING METHOD
Document Type and Number:
Japanese Patent JP2012095322
Kind Code:
A
Abstract:

To reduce processing delay by reducing an operation quantity in signal decoding.

A reception symbol and an output from a QR decomposing section 22 are supplied to a multiplying section 21, and the reception symbol is multiplied by the output from the QR decomposing section 22. A plurality of multiplying sections 21 and a plurality of QR decomposing sections 22 are provided depending on the number of sub-groups. The multiplying section 21 multiplies a conjugate transposed matrix by the reception symbol, thereby quadraturizing the reception symbol. A permutation channel matrix from an AGS section 23 is supplied to the QR decomposing section 22. A channel response matrix from a channel estimating section 14 is supplied to the AGS section 23. The reception symbols divided into a plurality of sub-groups from the multiplying section 21 and quadraturized are supplied to a local detector 24. The local detector 24 executes signal detection by hierarchical algorithm (e.g. M-algorithm) while utilizing each quadraturized sub-group.


Inventors:
HARADA HIROSHI
KIMURA RYOTA
Application Number:
JP2011271906A
Publication Date:
May 17, 2012
Filing Date:
December 13, 2011
Export Citation:
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Assignee:
NAT INST INF & COMM TECH
International Classes:
H04J99/00; H04B7/04; H04J11/00
Domestic Patent References:
JP2005176020A2005-06-30
JP2006203782A2006-08-03
JP2006121348A2006-05-11
Foreign References:
WO2005078955A12005-08-25
Attorney, Agent or Firm:
Masatomo Sugiura
Takuma Sugiura