Title:
SIGNAL DELAY ANALYZING METHOD FOR LIS DESIGN
Document Type and Number:
Japanese Patent JP3558514
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To determine in a short time an accurate signal propagation delay time in consideration of cross-talk in wiring in an LSI(large-scale integrated circuit).
SOLUTION: Certain wiring represented by an L-shaped circuit constituted of a wiring resistor Ri and a fixed grounding capacitor Ci, and an adjacent wiring is similarly separated by an L-shaped circuit constituted of a wiring resistor Rj and a fixed grounding capacitor Cj. Also, inter-wiring capacitences parasitic between both wirings are represented by variable capacities Cyij(t) and Cyji(t) connected to each wiring. These variable grounding capacitances vary as a function of time (t), and they are arranged so that exactly the same step response can be obtained in the circuit having the inter-wiring capacity and the circuit having the variable grounding capacity. Then, the accurate delay time of each node is calculated by repeated calculation using the rough delay value of each node as an initial value at time (t).
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Inventors:
Kazuo Tsuzuki
Masahiko Toyonaga
Masahiko Toyonaga
Application Number:
JP33974597A
Publication Date:
August 25, 2004
Filing Date:
December 10, 1997
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP10162045A | ||||
| JP8320896A |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Ichiro Oneda
Hiroshi Koyama
Ichiro Oneda