Title:
SIGNAL DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPH08125510
Kind Code:
A
Abstract:
PURPOSE: To realize a circuit obtaining a highly precise and stable delay signal in LSI.
CONSTITUTION: A decoder 20 which selectively outputs input signals is provided on latch circuits 21-24 obtaining delay quantity to be delayed with signals to be delayed as inputs. Plural latch circuits 21-24 giving clocks different in delay quantity from the external part of LSI as latch clocks and setting the output of the decoder 20 as input data are provided. Thus, the signal having target delay quantity is obtained through a gate 25 which OR-operates the outputs of the latch circuits.
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Inventors:
TAKEDA AKIHIRO
KOBAYASHI MINORU
KOBAYASHI MINORU
Application Number:
JP28287994A
Publication Date:
May 17, 1996
Filing Date:
October 21, 1994
Export Citation:
Assignee:
ADVANTEST CORP
International Classes:
H03K5/135; (IPC1-7): H03K5/135