PURPOSE: To attain signal delay without causing a phase error by providing a voltage control means to a power line of a CMOS gate circuit and using the control means to control a signal delay between the input and output of a gate circuit thereby controlling easily the delay time.

CONSTITUTION: A p-channel MOSFET16 and an n-channel MOSFET18 are inserted to the power line of a CMOS gate as delay time control elements. Control voltages v1, v2 are inputted respectively to gates of the FET16, 18 from terminals 20, 22. The control voltages v1, v2 are set symmetrically to reference potentials VDD-VSS. A CMOS inverter is constituted by controlling the values of the control voltages v1, v2. Voltages applied to a p-channel MOSFET12 and an n-channel MOSFET14 are changed to change the delay time.