PURPOSE: To increase the number of channels, by detecting an objective signal even if the start of the signal is unknown, through the comparison of full bits of data written in a shift register during the period from the write of a reception input signal to the shift register to the next write.

CONSTITUTION: Inverters 371, 372 are inserted to a shift register 32 in 32-bit to which a received and demodulated signal is applied via a D-type flip-flop 31 so as to obtain an output of each stage to be logically L level when an objective signal SC is written in each stage, and the register 32 is connected to one input of AND gates 380∼387. The other input of the AND gates is scanned with a clock 32-times the write clock of the shift register 32 with a scanning circuit 34. The output of an OR gate 39 is counted at a counter 35 and the output is taken as logically L level when the count value of the counter is 3 or more (error correction of maximum two can be done for the said signal SC). The SC detection signal (m) operates a detection circuit 36 for the reception of a selection call signal.