To provide a signal generating circuit which can reduce a jitter value of an output signal depending on data contents.
The signal generating circuit 34 generates a sub-clock signal which is generated based on a basic clock signal CLK1 and has the 1/2 frequency of the basic clock signal, a reversed sub-clock signal (/CLK2) which is reverted the sub-clock signal, an H level signal, and an L level signal. A control circuit 32 compares levels of the input signal Si inputted synchronizing to the base clock signal CLK1 and the output signal Si, and levels of the output signal Si and a sub-clock signal CLK2 at the time of the change of the basic clock signal CLK1, and outputs a control signal Sc which selects one out of the predetermined sub-clock signal, the reversed sub-clock signal, the H level signal, and the L level signal that are prescribed in advance following the comparison result. An output circuit 33 outputs selectively one out of 4 signals generated by the signal generating circuit 33 following the control signal Sc, and outputs respective signals as output signals.
Yoshiaki Naito
Cui Shu Tetsu